All the initial metrics of the business case are established to measure the problem scale [ 2 , 7 ]. Improve I : Post root cause analysis, this phase tries to understand optimum levels of factors responsible for causing the problem via design of experiments DOE , giving insights to determine corrective and preventative actions.
This stage involves lean strategies such as the Kaizen Blitz, poka-yoke mistake-proofing , cycle time reduction, etc. Control C : Primary objective in this last phase is to maintain and sustain control over the process and suggest improvement activities to minimize variation and defects. Statistical process control SPC , total productive maintenance TPM , and control plan development are some key tools used in the control phase [ 10 ].
In this section, some business process areas have been identified to focus on benchmarking before considering Six Sigma project execution. Once these business process areas are well established, then only deploying Six Sigma teams would be beneficial to see tangible results.
Motorola was one of the pioneers of Six Sigma methodology along with General Electric. Apart from Motorola, no other semiconductor manufacturing company has openly advocated the use of Six Sigma but has definitely inherited a lot of concepts and molded them into different terminologies.
A big challenge to Six Sigma implementation is management support, and based on historical success rates of such projects initiated at their respective firms, the management decides to stick to their existing problem-solving methodologies or use some concepts from Six Sigma and other techniques used in industries such as aviation and automotive. The most important goal for any semiconductor fab is to improve the final product yields [ 4 ]. Yield is directly correlated to contamination, design margin, process, and equipment errors along with fab operators [ 11 ].
Six Sigma DMAIC methodology can be used as an effective quality and reliability management tool to solve most of these issues, and several literature papers in the form of case studies have been published regarding the same. Sources of random defects could be the equipment, fab personnel, process margins, process chemicals and gases, or cleanroom itself. Data collected from Integrated Circuit Engineering Corp.
Human and cleanroom sources of contamination have been steadily declining due to advanced training in this field being developed over the years at various universities and corporations along with rapid strides in automation and artificial intelligence that have modernized clean rooms and minimized human contact in handling wafers.
Application of Six Sigma in Semiconductor Manufacturing: A Case Study in Yield Improvement
Engineers and upper-level management of these fabs must adopt a systematic methodology in resolving yield losses that occur due to process and equipment variations, and in this chapter, some basic business processes have been described that must exist in a fab for it to achieve maximum operational efficiency and produce high-quality chips. These fluids and gases contain impurity elements that can be dangerous to silicon devices [ 4 ].
These elements could be classified as the heavy metals, alkali metals, and light elements. Heavy metals such as Fe, Cu, Ni, Zn, Cr, Au, Hg, and Ag could result in wafer scraps and back end yield fallout due to corrosion in electroplating and metal deposition processing steps.
These elements also sometimes accumulate along the chambers, handlers, chucks, etc. Moreover, these elements could also pose safety problems to fab personnel.
To understand potential risks and sources of these impure elements, a highly cross-functional FMEA team can be deployed to map out all the processes where source chemicals and gases are used along with identifying potential fail modes, severity, occurrence, and detection capabilities. The RPN exercise can be continued to drive improvements at each processing step where such impure elements are likely to occur.
Defect density is defined as the total number of defects calculated per unit area on the wafer die [ 4 ]. In order to reduce defect density between processes, engineers need to identify the specific process steps, equipment, input materials, etc. This involves the construction of a detailed process flow diagram for isolated segments of the process and the use of various problem-solving tools such as using the Six Sigma concepts, cause and effect diagrams, design of experiments, Pareto principles, etc. Most cutting-edge fabs have automated scripts using machine learning principles to have correlation between in-line defects and final yield loss.
Advanced data mining software can quickly scan through very large data sets involving integrated circuit parameters, processing parameters, equipment parameters, probe bins, defect metrics, etc. Thus, having a good defect management and yield monitoring system while benchmarking to industry leaders will enable semiconductor fabs to execute Six Sigma projects efficiently while maintaining a competitive edge in the market. Another major factor controlling line and probe yields is the ability of the fab to control process variations on critical parameters.
In many progressive fabs, situational SPC is now becoming more popular as engineers concentrate more on critical processes and avoid the temptation to overuse tools such as process control charts. Two most important points that fabs must know regarding SPC charts to track in-line defects for Six Sigma scalability are: Due to the high number of processing steps and the possibility of defects forming from any source, fabs must have particle monitoring PMON charts which are effectively attribute charts that track defects per million opportunities DPMO on bare silicon wafers to plot particles coming from the equipment.
This helps to isolate defect sources solely coming from process equipment and can be tied with regular total productive maintenance TPM cycles in the fab. In-line defect metrology teams must be able to skillfully partition the line in placing SPC charts to control defect metrics based on historical learnings. Most fabs that do not have Six Sigma experts on their team usually have a hard time in determining the number of control charts and end up oversampling or undersampling.
Attribute charts for key defect metrics that have downstream product yield impact or customer reliability issues should be given the highest priority in establishing control charts. This section describes a case study wherein Six Sigma DMAIC methodology was used to tackle a probe yield issue due to an in-line defect contamination occurring in a lithography process step. This phase of the DMAIC methodology aims to define the scope and goals of the improved project in terms of customer requirements and to develop a process that delivers these requirements.
The first step toward solving any problem in the Six Sigma methodology is by formulating a team of people associated with the process [ 12 ]. For the case study in discussion, suspect of in-line process step was not known, and only the critical business impacting factor of yield loss data was known. The initial team comprised of a Certified Six Sigma Black Belt CSSBB who were the site quality engineering manager, yield engineering managers, failure analysis engineers, and technicians along with defect metrology engineers.
Next, the problem statement addressing CTQ and magnitude of the problem was identified. Failure analysis team was contacted to perform extensive cross-sectional analysis of the defect location. Based on the information available to the Six Sigma team at this stage, problem statement was defined as follows:.
Here, the CTQ metric of die yield loss could directly be correlated to the number of such defects forming during in-line manufacturing that cause poor yields which results in delayed shipments and dissatisfied customers. In this phase, data correlation was conducted to see the correlation between in-line defect counts per wafer to the number of failing dies per wafer at the final probe and percentage of edge die yield loss.
Six Sigma project team must reduce in-line defect count to less than 50 defects per wafer to have no die yield fallout at the final probe test. Regression plot of a number of failing die per wafer at final probe and b percentage edge die yield loss per wafer to number of defects per wafer in-line. The analysis phase consisted of searching through brainstorming rounds, the possible factors that may be affecting the electrical performance of the product. This stage of the Six Sigma process improvement methodology is often termed as Thought Process Mapping [ 13 ] wherein process experts and Six Sigma champions assimilate existing facts and data collected so far and look for initial trends and themes to find clues to go after.
The factors that were considered most important were raised as hypotheses and tested by several statistical tests. Wafer fabrication line is partitioned into three modules—front end of line FEOL , middle of line MOL , and back end of line BEOL —where each module involves complex steps such as lithography, thin-film depositions, etching, planarization, and diffusion. Inspection sampling plans are strategically placed across several processing steps within these three modules considering cost, cycle time, and wafer throughput times.
In this case, the project team was interested to see if there was any in-line defect inspection step that could replicate the defect pattern shown on probe bin wafer map.derlustbanbee.tk
Lean Six Sigma implementation: multiple case studies in a developing country | Emerald Insight
The project team decided to inspect additional sample wafers through this step and perform failure analysis on the defect locations. More in-line inspection recipes were set up strategically right after metal patterning lithography processes to study defect formation and evolution as the wafers progressed through manufacturing steps. Through in-line inspections set up across these modules, it was observed that the defect under study was first detected after the metal patterning process. This gave an initial indication to the Six Sigma team that metal patterning process and perhaps tool variation in lithography must be analyzed further.
There was a need for lithography experts to now help the Six Sigma team in root cause analysis, so lithography process engineering manager, two process engineers, and two process technicians were added to the project team. The project charter was revised to include the new members into the stakeholder team. Since there is a strong clue of the issue coming from the lithography process area, Six Sigma project team decided to add lithography process experts into the stakeholder team.
Gemba revealed that there was only one resist supplier to the patterning process, so supplier variation is not a root cause. SEM imaging did not reveal any polymer shearing defects. DOE carried out on resist coating process included a multilevel factorial design where coating speeds were varied from low to high to see if defects could be produced, but it was not the case. Fab contamination studies also showed that particles were well within control and environmental impacts to the formation of in-line defects were negligible. Careful review of all SOPs, manufacturing protocols, preventative maintenance log books, shift pass-downs, etc.
Majority of the effort was then spent in analyzing tool-to-tool variation, which was performed by ANOVA. There were three major tools in the factory running this product line, which will be addressed as Tools 1, 2, and 3 for analysis.
Six Sigma @ the Edge
Tool 1 mean value was not only above the target defect count value of 50 but was also significantly above Tools 2 and 3, clearly indicating a problem with this tool. Since there are multiple tool sets and data is non-normal, the Wilcoxon method is used for multiple tool set comparisons [ 14 ]. H o : Tool 1 toggle is statistically insignificant; H a : Tool 1 toggle is statistically significant. It is observed that p-value is less than 0. Based on Wilcoxon test, reject H o and accept H a. Therefore, Tool 1 toggle is statistically significant and the toggle to defect metric is real.
Next, the project team was tasked to look at SPC charts of all critical parameters of all three tools. SPC charts and normal quantile plots reveal a significant drift in parameter settings for Tool 1 compared to Tools 2 and 3.
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SPC charts show very tight distribution of points for Tools 2 and 3, but Tool 1 is not only out of spec but also has high amount of wafer-to-wafer variation for scanner speed and exposure dosage. Out of all the possible failure modes evaluated and tested, it was confirmed that the source of defect could possibly be coming from Tool 1 metal pattern processing step in lithography area due to significant variation in scanner speed and exposure dosage.
The theory behind defect formation due to inaccurate scanner speed and exposure dosage is described below which is a commonly observed phenomenon in the industry [ 14 ]. This defect is caused by a bubble forming in the scanner just prior to exposure. Light passing through the air bubble instead of the immersion water causes light refraction which creates a dipole. The space between wafer and immersion hoods where the light source is located is filled with water as an immersion fluid to increase image resolution by a fraction equal to the refractive index of the fluid [ 14 , 15 , 16 ].
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